The present invention relates to a method of producing a high-resistivity silicon wafer. More particularly, the present invention relates to a method of producing a high-resistivity silicon wafer which exhibits minimal change in resistivity upon heat treatment during device processing and which has reduced density and reduced size of defects.
High resistivity silicon wafers have conventionally been used for power devices such as high-voltage power devices and thyristors. More recently, C-MOS devices, Schottky barrier diodes, and other semiconductor devices for use in mobile communications have been developed which require the use of high-resistivity silicon wafers. The high-resistivity wafers tend to decrease the effects of parasitic capacitance among the devices of the wafer, allowing the devices to be more closely packed upon the surface of the wafer while, at the same time, reducing signal transmission loss among the devices.
High-resistivity wafers are generally defined as those silicon wafers with resistivity of 100 xcexa9xc2x7cm or greater, and typically have resistivity of 1000 xcexa9xc2x7cm or greater. The initial resistivity of a wafer is established during crystal growth by the precise addition of dopants to the molten polysilicon from which the silicon crystal is formed. By doping, the resistivity of the crystals can be controlled within close tolerances. However, the initial resistivity may be altered, desirably or undesirably, during subsequent processing of the wafer such that the final resistivity of the wafer may be very different from the resistivity directly after crystal growth.
In order to form more devices from a single wafer and therefore reduce the cost per device, larger wafers are generally preferred. As such, while high resistivity silicon wafers may be fabricated by a float zone technique, the limitations on size of the resulting wafers make the Czochralski (CZ) crystal growing method the desired fabrication technique. The CZ method allows wafers having diameters of 200 mm, 300 mm, 400 mm, or larger to be produced. In addition to the large wafer diameter, the CZ method also provides wafers with excellent planar resistivity distribution. Good planar resistivity distribution means that the wafer has only minimal variations in resistivity along the plane which was perpendicular to the direction of pull of the crystal during crystal growth.
Unfortunately, there are some problems related to the presence of oxygen during the growth of high-resistivity silicon wafers in a CZ apparatus. During crystal growth within a CZ apparatus, oxygen from the quartz crucible tends to be introduced into the silicon crystal and is maintained in the interstitial spaces of the silicon crystal lattice. The interstitial oxygen atoms are normally electrically neutral, but the oxygen atoms tend to agglomerate as oxygen-containing thermal donors (OTDs), which become electron donors when subjected to heat in the range of 350xc2x0 C. to 500xc2x0 C. Thus, the resistivity of the wafer may be unfavorably decreased by a relatively mild heating due to the contribution of electrons from the OTDs residing in the wafer. The decrease in resistivity due to the oxygen is especially problematic considering that temperatures in the range of 350xc2x0 C. to 500xc2x0 C. are commonly encountered during process steps subsequent to wafer fabrication, such as during device fabrication.
The elimination of oxygen from the silicon lattice is not a complete solution to the problem of resistivity variation within a silicon wafer. The presence of oxygen within the silicon crystal causes bulk defects to form within the crystal. Though large numbers of bulk defects are not desired, small numbers of bulk defects contribute to a gettering effect within the crystal. By gettering, the defects within the crystal act to trap mobile ionic contamination and to prevent the contamination from traveling to the surface of the wafer. The gettering is necessary to protect the devices on the surface of the wafer from interference from the contaminants. Thus, some oxygen within the wafer is desirable, although too much oxygen is disadvantageous and tends to decrease the resistivity of the silicon wafer.
Further to the concerns of oxygen being present within the wafer, the grown crystal is also likely to contain grown-in defects such as Flow Pattern Defects (FPD), Laser Scattering Tomography Defects (LSTD), Crystal Originated Particles (COP), Large Secco Etch Pit Defects (LSEPD), and Large Flow Pattern Defects (LFPD). It is considered very important to reduce the density and the size of the defects.
Generally speaking, there are two predominant types of defects within the growing crystal, a void type point defect called vacancy, abbreviated as V, and an interstitial type silicon point defect called interstitial silicon, abbreviated as I.
A V region in a silicon single crystal is a region containing many vacancies, such as depressions, pits, voids, and similar defects generated due to missing silicon atoms. V region defects include FPD, LSTD, and COP defects. An I region is a region containing many dislocation and aggregations of excessive silicon atoms generated due to excessive amounts of silicon atoms within the lattice. I region defects include LSEPD and LFPD defects. Between V regions and I regions, there exist neutral regions, abbreviated as N, which have no vacancies or interstitial silicon.
When the pull rate of the crystal is relatively high, a V region is found across the entire radial cross-section of the growing crystal. When the pull rate is decreased, a ring called the OSF, or Oxidation Induced Staking Fault ring, forms at the circumference of the growing crystal. As the rate of crystal pull is reduced, the OSF moves from the radial circumference of the growing crystal ingot toward the center, with the portion of the crystal laying between the OSF and the outer circumference of the crystal being an I region. At low pull rates, the OSF approaches the center of the cross-section of the growing crystal and eventually disappears, leaving the entire cross-section of the growing crystal as an I region.
It has been discovered that a region called the neutral region, or N region contains neither vacancy type defects nor interstitial type defects. The N region is present between the V region and the I region, outside of the OSF ring. The size and the orientation of the N region varies with the parameter of v/G, which is the ratio of the pulling rate of the crystal, v, and the crystal solid-liquid interface temperature gradient, G, along the growing axis.
Through variation of the pulling rate and/or temperature gradient, the v/G ratio may be optimized to produce a crystal having the N region spreading over the entire transverse cross-section of the crystal, for example, when the crystal is pulled with a gradually decreasing pulling rate, v. An N region which spreads over the entire transverse cross-section does not contain grown-in defects at all.
What is needed is a method of producing high-resistivity silicon wafers having a reduced interstitial oxygen content, having sufficient precipitated oxygen to provide effective gettering within the body of the wafer, and having low in-grown defect content.
The invention is a method of treating a high-resistivity silicon wafer containing interstitial oxygen in such a way that the oxygen is largely precipitated, which prevents the oxygen from acting as an electron donor and prevents the resistivity of the wafer from diminishing. The method simultaneously minimizes the density and size of in-grown defects within the high-resistivity silicon wafer.
A method of obtaining a wafer exhibiting high resistivity and high gettering effect while preventing the reduction of resistivity due to the generation of oxygen thermal donors, and while further minimizing in-grown defects is provided by: a) using a CZ method to grow a silicon single crystal ingot having a resistivity of 100 xcexa9xc2x7cm or more and an initial interstitial oxygen concentration of 10 to 40 ppma with a v/G ratio from about 1xc3x9710xe2x88x925 cm2/sxc2x7K to about 5xc3x9710xe2x88x925 cm2/sxc2x7K, b) processing the ingot into a wafer, and c) subjecting the wafer to an oxygen precipitation heat treatment whereby the residual interstitial oxygen content in the wafer is reduced to about 7 ppma or less.
The resulting wafer has high resistivity, increased gettering ability, and is resistant to slip dislocations. Further, the wafer contains no grown-in defects. Precipitation of the interstitial oxygen content prevents the oxygen constituents from becoming electrically active thermal donors upon subsequent heat treatments of the silicon wafer, such as during device installation. Thus, a consistent wafer resistivity may be maintained without undue change caused by undesirable electron donation from oxygen content within the wafer.